1. Field of the Invention
The present invention relates to a power-up circuit, and more particularly, to a power-up circuit for a semiconductor memory device.
2. Description of the Related Art
Power-up circuits are often included in integrated circuit chips for providing a power-up pulse that initializes the different portions of the circuit when a supply voltage is applied to the chip. For example, in a computer system, many electronic devices in the system, such as a memory device, need to be driven to an initial condition prior to being used after the computer system is turned on or reset. A typical memory device has memory cells which use a variety of logic circuits such as latches and flip-flops to support their operation. These logic circuits need to be driven to an initial condition before the memory device is used to store data. As such, a power-up circuit is used to ensure that the logic circuits are initialized without floating gate nodes that could lead to excessive power consumption or unknown states.
A typical design of a power-up circuit is a resistor-capacitor (RC) time delay circuit connected to an input of an inverter. When a supply voltage is first applied to the delay circuit, the capacitor starts to charge. Upon starting the charging process, the inverter outputs a signal at a logic high level. When the capacitor is sufficiently charged to generate a logic high level, the output of the inverter switches to a logic low level. The time interval between the logic high and logic low levels of the output of the inverter defines a power-up pulse for driving the logic circuits in the integrated chip. Although the conventional RC time delay circuit is generally suitable to provide a power-up signal, it is problematic in the case of a slow-rising supply voltage. When the supply voltage ramps up relatively slowly compared with the charging rate of the capacitor, the power-up pulse may not be generated, and power-up failure will occur.
FIG. 1 shows a power-up circuit disclosed in U.S. Pat. No. 6,097,659. The power-up circuit includes an external supply voltage level detector 100, an internal supply voltage level detector 200, and a power-up signal generator 300. The detector 100 is configured for detecting an external supply voltage level and generating a detection signal PUPB1 when a first predetermined voltage level is detected. The detector 200 is configured for detecting an internal supply voltage level and generating a detection signal PUPB2 when a second predetermined voltage level is detected. The power-up signal generator 300 is configured for receiving the detection signals PUPB1, PUPB2 and generating a power-up signal SETB. Because the detection signals PUPB1, PUPB2 are independent from each other, this circuit may have a problem with various supply voltage rising sequences.
Accordingly, there is a need to provide a power-up circuit that can set the initial condition correctly. The power-up circuit should also have the ability to adjust trigger points of voltage potentials of supply voltages so that a power-up signal can be maintained long enough to ensure that logic circuits in a memory device are driven to initial conditions adequately.